1. Field of the Invention
This invention relates to a field effect transistor (FET), specifically to a structure of a field effect transistor which is suitable for integration, and has high outputs and gains.
2. Related Background Art
Recently accompanying the rapid development of information network systems, the needs for direct broadcast satellite communication systems as well is on increase, and the frequency band is becoming higher. High frequency FETs, especially GaAs metal-semiconductor FETs (MESFETs) are practiced as transistors which can make a break through the characteristic limit of the conventionally used Si bipolar transistors. Recently for the miniaturization, lower prices and higher performance of the systems, the integration of the first stage amplification circuits of a downconverter that converts a high frequency signal to a low frequency signal is advanced and the circuits are formed as microwave monolithic integrated circuits (MMIC's).
To achieve higher output and higher efficiency of the GaAs MESFET, it is important to reduce a resistance between the source electrode and the gate electrode, i.e., the source resistance (Rs) to thereby increase the transconductance (g.sub.m), and, at the same time, to increase the drain voltage resistance between the gate electrode and the drain electrode. In view of this, as described in Japanese Patent Laid-open Publication No. 177779/1986, the usual high-output MESFETs use the structure of FIG. 1 for decreasing the source resistance Rs. That is, a gate structure which is called recess structure is used. In the recess structure, a recess 3 of a given depth is provided between the source electrode 1 and the drain electrode 2, and the gate electrode 4 is formed on the bottom surface of the recess 3. Furthermore, for increasing the drain voltage resistance, the gate electrode 4 is offset nearer to the source electrode 1 so that distance between the gate electrode 4 and the drain electrode 2 becomes wide.
But in such device structure, for example, in an n-channel MESFET, a phenomenon called long gate effect occurs where a gate bias is lower, i.e., where the gate voltage has a negative value, and its absolute value is smaller. This long gate effect is a phenomenon that an effective gate length increases due to a surface depletion region on the side of the drain electrode 2. This phenomenon is reported in good detail in The Institute of Electronics Information and Communication Engineers (AED86-142, 1986). It is known that the transconductance g.sub.m lowers due to this long gate effect. As means for improving the long gate effect, the MESFET of the structure of FIG. 2 was disclosed in Japanese Patent Laid-Open Publication No. 260861/1989. That is, a recess 8 is formed in an operational layer 7 between a source electrode 5 and a drain electrode 6, a gate electrode 9 is formed on the bottom surface of the recess 8, and the recess 8 has the stepped sidewall nearer to the drain electrode 6. This two-step sidewall prevents the long gate effect.
On the other hand, there is a high-frequency MESFET having a gate electrode region of a planar structure without such recess structure. In this MESFET, the ion implantation of dopant ions is performed by utilizing self-alignment using the gate electrode as a mask in order to reduce the source resistance of the operational layer. The integration of this MESFET with the gate electrode region of such planar structure is reported in GaAs IC Symposium Technical Digest (1987), pages 45 to 48 and pages 49 to 52. In addition, there is a MESFET having a gate electrode region of such planar structure which was developed by the applicant of the present application, and this MESFET is described in IEEE MTT-S International Microwave Symposium Digest, 1990, pages 1081 to 1084. In this MESFET, an epitaxial wafer of a pulse-doped structure having a thin channel layer of a higher carrier density, and a cap layer of a lower carrier density formed on the channel layer is used. The integration of this planar-structure FET having such pulse-doped structure is disclosed in GaAs IC Symposium Technical Digest, 1990, pages 237 to 240.
But the respective conventional FETs described above have the following technical problems. The MESFET with the recess structure of FIG. 2 has solved the occurrence of long gate effect intrinsic to the recess-structure FET of FIG. 1, but because of the recess-structure intrinsically formed in the gate electrode region, the homogeneity and reproductivity of the manufactured FETs are not good. This results from poor controllability of the recess etching in forming recesses 3, 8, which causes deviations of an etched depth. In integrating especially such MESFETs on semiconductor substrates as high-output integrated circuit devices, the yield becomes low, the productivity becomes low.
On the other hand, the planar-structure MESFET without such recess structure in the gate electrode region is free from the above-described problems involved in homogeneity and reproductivity resulting from the recess etching, but has the same problem as the recess-structure FET of FIG. 1. That is, for higher output and higher drain voltage resistance of the FET, as described above, the gate electrode is offset apart from the n.sup.+ ion added layer nearer to the drain electrode. But in this structure, as described above, long gate effect adversely occurs where a gate bias is lower, and the transconductance g.sub.m adversely lowers. Furthermore, the MESFET having such planar-structure gate electrode region has not been able to find effective preventive means owned by the recess-structure MESFET, i.e., the effective means that the sidewall of the recess has two steps as in FIG. 2.